Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones, among others. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, and other electronic devices.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged.
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell in a “row” of the array are coupled to an access line (which is commonly referred to in the art as a “word line” or “select line”). However each memory cell is not directly coupled to a column data line (which is commonly referred to in the art as a “bit line” or “sense line”) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column sense line.
Memory cells in a NAND array architecture can be programmed to a desired state. That is, electric charge can be placed on or removed from the floating gate of a memory cell to put the cell into a number of stored states. For example, a single level cell (SLC) can represent two states, e.g., 1 or 0. Flash memory cells can also be programmed to more than two states, such as to a number of states that allows a cell to represent more than two binary digits, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multi state memory cells, multidigit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one binary digit, e.g., more than one bit. MLCs can have more than two programmed states, e.g., a cell capable of representing four digits can have sixteen programmed states. For some MLCs, one of the sixteen programmed states can be an erased state. For these MLCs, the lowermost program state is not programmed above the erased state, that is, if the cell is programmed to the lowermost state, it remains in the erased state rather than having a charge applied to the cell during a programming operation. The other fifteen states can be referred to as “non-erased” states.
Flash memory devices can be programmed with various amounts of data at one time. The amount of data programmable at one time can be referred to as a page of data. In some memory devices, one page of data includes data stored on memory cells coupled to a given select line. In other memory devices, data stored on a select line can be divided into more than one page, e.g., into an even page and odd page of data. In some instances, a page of data may include data stored in memory cells on more than one select line. Various amounts of data can also be erased from a flash device at the same time. The amount of data erasable at one time can be referred to as a block of data. A block of data can include a number of data pages. A memory plane can include a number of data blocks on a given die. Some memory devices have multiple planes per die. For example, a die could include a plane of even numbered blocks and a plane of odd numbered blocks.
During a programming operation, data can be loaded into cache registers for each memory plane before being programmed to each plane. For example, a page of data may be loaded into a register, then programmed to a plane, after which another page of data may be loaded into the register. This process can repeat until the programming operation completes. During a sensing operation, data can be loaded from one or more memory planes into cache registers.
Currently, the de facto standard interface for NAND flash memory utilized by major NAND flash memory manufacturers is an asynchronous interface. The asynchronous interface has supported several generations of scaling of the input/output (I/O) data rates. However, the scaling limit of the asynchronous interface is fast approaching, and a memory access device will have difficulty in cleanly capturing data from the memory, e.g., NAND Flash, device at higher access speeds.